As a next generation nonvolatile memory realizing high speed performance and high levels of durability in rewriting, memories using magnetic tunnel junction (MTJ) elements, which are variable resistance memory elements, have drawn attention.
For using MTJ elements as the memory element, it is necessary to use a combination of an MTJ element and a selection device for selecting the MTJ element. As the selection device, N-type metal oxide semiconductor field-effect transistors (MOSFETs), P-type MOSFETs, complementary metal oxide semiconductors (CMOSs), and the like are used.
FIG. 23 shows the circuit configuration of a unit cell when the selection device is an N-type MOSFET 10a. Here, the bottom pin structure in which the N-type MOSFET 10a is connected to a pin layer 53 of an MTJ element 50 is used. A given voltage is applied to either one of a terminal 1 and a terminal 2 and the other terminal is grounded. As a voltage Von as a selection signal is applied to the gate of the N-type MOSFET 10a and the N-type MOSFET 10a is turned on, a current flows through the MTJ element 50 and data corresponding to the direction of the current flowing through the MTJ element 50 are written.
However, when the terminal 1 is grounded and a positive voltage is applied to the terminal 2, the N-type MOSFET 10a works in the saturation region; therefore, a current sufficient for rewriting the MTJ element 50 does not flow in the direction from the pin layer 53 to the free layer 51. Generally, a current that should flow from the pin layer 53 to the free layer 51 for switching the MTJ element from the parallel state to the antiparallel state is larger than a current that should flow from the free layer 51 to the pin layer 53 for switching from the antiparallel state to the parallel state. Therefore, the above situation is significantly disadvantageous from the viewpoint of the MTJ switching.
It is possible to use the top pin structure instead of the bottom pin structure. However, creating the top pin structure itself is difficult. Therefore, it is difficult to use the top pin structure both with the N-type MOSFET 10a and with a P-type MOSFET 10b. 
FIG. 24 shows a circuit configuration when the selection device is a P-type MOSFET 10b. Here, the bottom pin structure is used. As the gate of the P-type MOSFET 10b is grounded and the gate of the P-type MOSFET 10b is turned on/off, a current is supplied/not supplied to the MTJ element 50.
However, when a terminal 3 is set to the ground potential, a terminal 2 is grounded, and a positive voltage is applied to a terminal 1, the P-type MOSFET 10b works in the saturation region. Therefore, a current sufficient for rewriting the stored data of the MTJ element 50 does not flow in the direction from the free layer 51 to the pin layer 53. In this situation, unlike the N-type MOSFET, the current necessary for switching the MTJ element and the current that can be flowed through the MOSFET well match in asymmetricity. However, a problem is that a P-type MOSFET is intrinsically low in the ability of current supply compared with an N-type MOSFET.
Moreover, as a case in which a CMOS is used as the selection device, Non-Patent Literature 1 discloses a nonvolatile flip-flop circuit including an MTJ element. Since a CMOS comprises a combination of an N-type MOSFET and a P-type MOSFET, it is possible to path a current symmetric in both directions through the MTJ element.